Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed- signal macros. A critical example of such a support circuit is the phase locked loop (PLL). The realization of the PLL using a traditional analog architecture places demands on the underlying process technology that are quite different from those driven by high speed logic requirements. Analog PLLs typically require elements not used in standard logic, including resistors and low leakage capacitors, and rely on properties not critical to standard logic circuits, such as matching and output impedance uniformity. Furthermore, analog PLLs may use logic families other than static CMOS, such as current mode logic (CML). As process technologies advance and grow in complexity, the challenge of maintaining required analog elements and performance for use in circuits such as PLLs grows. Furthermore, because the analog PLL uses elements, device properties, and logic families unlike those of the chips digital core, its yield and performance spreads may not be well-correlated to those of the digital portions of the design. Key DPLL design issues include how the phase error between reference and feedback clock is quantified, the structure of the loop filter, whether an analog (via digital-to-analog conversion of the filter output) or direct digital control of the VCO is used, and the choice of oscillator topology. A number of digital PLLs have been described in the literature, with target application spaces ranging from microprocessors to cellular telephone chipsets. In above figure Power7 microprocessor architecture with eight cores and their associated L2 and L3 caches connected to each other through an asynchronous, memory coherent bus i shown. Each core can run at its own speed as a direct result of DPLLs employed. Core frequency is centrally managed to optimize for performance and power dissipation.
Posted on: Mon, 15 Sep 2014 02:08:56 +0000
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