Intel’s 14nm Broadwell chip reverse engineered, reveals impressive FinFETs, 13-layer design When Intel announced the details on its 14nm process last year, it raised eyebrows in some circles by claiming some extremely aggressive scaling figures. Put simply, Intel stated that it would deliver a better 14nm process with superior characteristics, die size, and overall efficiency than any competitive product TSMC, its largest foundry competitor, would release on 20nm. This predictably kicked off a PR blizzard between the two companies. Intel stated that it would bring 14nm in with substantial scaling in transistor fin pitch, transistor gate pitch, and interconnect pitch, with a further significant reduction in SRAM scaling. Now, independent analysis and reverse engineering from Chipworks has confirmed that Intel did indeed deliver on its technological promises. Gate pitch has been measured at ~70nm, fin pitch at ~42nm, and a more complex 13-layer metal design. Intel had previously stuck with nine-layer designs before stepping up to 11 for its Bay Trail SoC. Metal layers inside a chip are used to connect various features and areas of the chip. As chips have gotten smaller it’s become increasingly difficult to route wires in ways that don’t obviate the increased performance of the transistors themselves. Intel’s decision to step up to a 13-layer design may be partly responsible for Broadwell’s difficulties; the more metal layers you have to connect the more difficult it is to design the chip efficiently. The one potential slip that Chipworks notes is that while Intel claimed a 52nm interconnect pitch, they measured 54nm — but they also say that this is within the margin of measurement error, and that Intel may have simply measured from a different point of the die. They also confirm that Intel hit its SRAM cell target size of 0.058 µm2. Like:facebook/MyItTurn Join:facebook/groups/myitturn
Posted on: Sat, 01 Nov 2014 10:47:36 +0000
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