Okay: I’m going to post a bit of a technical rant, but I hope you don’t mind. For the past several months, I’ve been exploring a number of problems that can be solved via extremely high-performance computing machines (or a network of them). They surpass what can be solved on a typical CPU (or even a few thousand of them) and require implementation on massively parallel hardware, such as what you might find in a GPU (Graphics Processing Unit) or FPGA (Field-Programmable Gate Array). These are silicon devices that aren’t built around the standard sequential processing paradigm inherent in a typical processor. To that end, I purchased first a Digilent Atlys FPGA development board in February, and a brand new Digilent Nexys-4 development board last week. Both are based on Xilinx FPGA chips (the Spartan-6 and Artix-7, respectively). The hardware is capable of performing extremely high-speed parallel calculations that can be quite complex. The downside is that you are currently forced to use antiquated hardware design languages to program the FPGAs, such as Verilog, System Verilog or VHDL. Although these languages loosely resemble traditional imperative languages (C for Verilog or System Verilog, and ADA for VHDL), these imperative language styles are ill-suited towards building what are typically little state machines that connect together. Although it’s relatively straightforward to build state-machines by themselves, it ends up being very tricky to connect a series of independent state machines so that all the clocking and data transfers work correctly. What I’d really like to see is a language that inherently thinks in terms of state, and transitions from one state to another, and builds these circuits for me. I’ve been looking at adapting one state-machine pre-processing language, Ragel, so that I could communicate state machine designs to it and it could spit out Verilog implementations that would translate to silicon designs. But it is still ill-defined how independent state machines would connect and communicate with one another. For example, I’ve written Verilog code that can run Collatz Conjecture tests (tests of the 3x+1 problem) very quickly; testing several million numbers per second using hand-coded parallel processors on a single FPGA. But then I also want to display information about the running processes using the on-board 7-segment display (eight digits on the Nexys-4), or VGA (Nexys-4) or HDMI (Atlys) video connectors. That involves building a whole separate state system, and the wiring to connect the output mechanism with my free-running processors. Oh; and one set runs at 50MHz while the other runs at 108MHz (for 1920x1280 VGA; different frequencies for HDMI, 7-segment display, or other VGA resolutions), and you’ve got some buffering issues between those two “time zones”. Bret Victor, in this video below, pointed out that during the 1960s and 1970s there was a period of revolutionary thinking about what programming COULD be, since it was largely before high-level languages had become a reality (COBOL and FORTRAN can’t really be considered high-level — they save you from programming in assembly language, but they’re quite low-level). Furthermore, imperative (procedural) programming have become so ubiquitous that we’ve fallen into a somewhat dogmatic way of thinking about what programming could be to make best use of programmable silicon structures, such as those on FPGAs. I’m not the first one to consider this problem, and I’m not likely to be the one to propose a solution for how to optimally design code to run on an FPGA chip or a massively parallel network of processors, but I think that the solution will be to design a language that simplifies the task not only of writing a state-machine (such as Ragel and a few languages do), but also to connect them together to design larger synchronous and asynchronous computing structures. Bret Victor’s talk focusing on communicating state machines: Ragel State Machine Compiler: Product info on those two Digilent FPGA development boards: Atlys: Nexys-4:
Posted on: Fri, 10 Oct 2014 03:40:55 +0000
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