09.04.2013/KOA-5 BALAMURUGAN KANNAPPAN / EEE (1997-2001) Senior Staff – IC Design, Broadcom, Bengaluru. (Nov 2006 - Till now) Higher Education: P.G.D.VLSI, (2001 – 2002) at Sandeepani School of VLSI Design Work Experience: MTS - Network Programs / Onsite: HITACHI-IT, Japan (Feb 2006 to Sep 2006) • Extracting the functionalities from the SAS specification. • Responsible for developing the High-level design, designing the Link Layer and providing the debugging support at the full chip level for GEMAC. • Code conversion for JPEG Compressor core modules. Senior Design Engineer at Innovative Logic (July 2005 – February 2006 ) • Extracting the functionalities from the WUSB specification. • Responsible for RTL Coding of the Wireless USB Function IP Core Sub Modules. Design Engineer at SONA VEDIC R&D, Sona College of Technology (January 2004 – July 2005) • Responsible for RTL Coding and Verification of the various USB Function Core Sub Modules and mentoring the new resources. • Designed the Prototype Board for the Multi-Lingual Digital Organizer Project. • Subjects Taught: Embedded Architecture and High Performance Networks. • Placement in charge of IT Department. • Mentoring the students for their final year projects. Research Associate at SONA EEE R&D, Sona College of Technology (December 2002 – December 2003) • Responsible for RTL Coding and Verification of ATM Cell Delineation Core Modules. • Part of a 5-member team responsible for feasibility analysis of the Multi-Lingual Digital Organizer project. • Providing the training in Verilog HDL Language and Fundamentals of FPGA Design. • Mentoring the students for their mini projects. Skills & Expertise: Functional Verification Verilog FPGA Debugging Perl Embedded System ASIC RTL coding https://facebook/balamurugan.kannappan.1?fref=ts
Posted on: Wed, 25 Sep 2013 05:50:21 +0000
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