Hello All , STMIcroelectronics ,Greater Noida is hiring...There are 50 positions.. ONLY FOR EXPERIENCED PEOPLE.. Please find below the details and send your resume to : rishabh.bansal@st In the mail dont forget to mention the Position title for which you want to apply.. Send your resume only if you are not referred by anybody in the past... atleast in past 6 months.. 1) Position title: Front End Design Engineer Position Description: Design of Digital IPs and SoCs. Responsibilities include the following for digital modules for highly complex SoCs/ASICs targeted towards Automotive applications: Complete Digital Design task-flow (specs. and micro-architecture definition, RTL coding, RTL rule checking, logic equivalence checking, IP integration, etc.. Support to Validation and Applications teams and customers Must Have Skills: • Digital micro-architecture definition & design partitioning • RTL (Verilog/VHDL) coding • RTL code quality and rule checks • Exposure to Synthesis & STA will be a plus • Technical troubleshooting and demonstrated problem solving skills • Team player, flexible, good communicator Good to Have Skills • Knowledge of coverage driven verification (System Verilog, uVM, etc.) and/or assertion based verification is desired Experience & qualification: 2 to 5 years of Experience and B.Tech/M.Tech. ( Electronics ) 2) Position title: Back End Design Engineer Position Description: The incumbent will be involved in design Implementation (RTL2GDII flow) of products related to Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for futuristic cars from the stable of leading car manufacturers ( Eg-Daimler,-Benz, BMW, VOLVO). Apart from the obvious challenge of reducing Area, mask re spin, consumption and increasing performance, other challenges include complying to ASIL-D safety standard, striving for zero PPM, crypto subsystem leveraging e-Flash etc Must Have Skills: • Knowledge of full RTL to GDSII flow ( Synthesis, STA, Floorplan, CTS, PnR, DRC/LVS, SI, IR Drop ) • Hands-on experience with Synopsys and Cadence Synthesis/STA and/or PnR tools • Should have good understanding of Verilog/VHDL • Exposure to low power techniques • Knowledge of Tcl and Perl scripting is a must Experience & qualification: 3 to 7 years of Experience and B.Tech/M.Tech. ( Electronics ) 3) Position title: DFT Engineer Position Description: Responsible to implement complete design testability cycle from architecture to silicon testing. To ensure adherence to corporate and automotive Testability targets by defining, planning and executing complete flow of DFT, ensuring high coverage, complete Testability, support to failure analysis and Silicon support to reach Maturity targets Must Have Skills: • Good RTL(VHDL or Verilog or system verilog) writing skills and/or the ability to create environment using the industry standard tools like Tetramax, Testcompress, RTL compiler, Design Compiler, etc. • Clear concept about scan based design. • Knowledge on ATPG and different Fault Models (SA, Transition, Iddq , SDD etc) • Coverage improvement techniques • SOC integration and RTL modification as per DFT requirement. • Usage of any one of the industry standard DFT tool (Tetramax, Testcompress, RTL compiler etc) • Basic knowledge of following : o synthesis constraints , o ATE o Silicon defects and its logical effects • Awareness of Latest technique viz. Scan compression, Analog Bist, Logic Bist would be appreciated and preferred. Experience & qualification: 3 to 7 years of Experience and B.Tech/M.Tech. ( Electronics ) 4) Position title: Verification Engineer Position Description: Verification of Digital IPs and SoCs. Responsibilities include the following for digital modules for highly complex SoCs/ASICs targeted towards Automotive applications. Complete Digital Design Verification task-flow. Verification at IP and SoC level . Support to Validation, Engineering and Applications teams and to ST customer Must Have Skills: • Digital micro-architecture definition & design partitioning • RTL(Verilog/VHDL/SystemVerilog,eSpecman) coding • RTL code quality and rule checks • Testbench and Verification Suite development • To implement coverage model and various coverage checks e.g. functional and assertion coverage. • Knowledge of various verification methodologies e.g.SVBCL, eRM, uRM, IFV, UVM etc. • Good Knowledge of C,C++ • Technical troubleshooting and demonstrated problem solving skills • Team player, flexible, good communicator Experience & qualification: 2 to 5 years of Experience and B.Tech/M.Tech. ( Electronics )
Posted on: Wed, 16 Jul 2014 08:27:27 +0000
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