dpsd question bank 1. (a) Explain how you will construct an (n+1) bit Gray code from an n bit Gray code (b) Show that the Excess – 3 code is self -complementing 2. (a) Prove that (x1+x2).(x1’. x3’+x3) (x2’ + x1.x3) =x1’x2 (b) Simplify using K-map to obtain a minimum POS expression: (A’ + B’+C+D) (A+B’+C+D) (A+B+C+D’) (A+B+C’+D’) (A’+B+C’+D’) (A+B+C’+D) 3. Reduce the following equation using Quine McClucky method of minimization F (A,B,C,D) = _m(0,1,3,4,5,7,10,13,14,15) 4. (a) State and Prove idempotent laws of Boolean algebra. (b) using a K-Map ,Find the MSP from of F= _(0,4,8,12,3,7,11,15) +_d(5) 5 (a) With the help of a suitable example ,explain the meaning of an redundant prime i implicant (b) Using a K-Map, Find the MSP form of F= _ (0-3, 12-15) + _d (7, 11) 6 (a) Simplify the following using the Quine – McClusky minimization technique D = f(a,b,c,d) = _ (0,1,2,3,6,7,8,9,14,15).Does Quine –McClusky take care of don’t care conditions? In the above problem, will you consider any don’t care conditions? Justify your answer (b) List also the prime implicants and essential prime implicants for the above case 7 (a) Determine the MSP and MPS focus of F= _ (0, 2, 6, 8, 10, 12, 14, 15) (b) State and Prove Demorgan’s theorem 8 Determine the MSP form of the Switching function F = _ ( 0,1,4,5,6,11,14,15,16,17,20- 22,30,32,33,36,37,48,49,52,53,56,63) 9. (a) Determine the MSP form of the Switching function F( a,b,c,d) =_(0,2,4,6,8) + _d(10,11,12,13,14,15) (b) Find the Minterm expansion of f(a,b,c,d) = a’(b’+d) + acd’ 10 Simplify the following Boolean function by using the Tabulation Method F= _ (0, 1, 2, 8, 10, 11, 14, 15) 11 State and Prove the postulates of Boolean algebra 12 (a) Find a Min SOP and Min POS for f = b’c’d + bcd + acd’ + a’b’c + a’bc’d 13 Find an expression for the following function usingQuine McCluscky method F= _ (0, 2, 3,5,7,9,11,13,14,16,18,24,26,28,30) 14 State and Prove the theorems of Boolean algebra with illustration 15 Find the MSP representation for F(A,B,C,D,E) = _m(1,4,6,10,20,22,24,26) + _d (0,11,16,27) using K-Map method Draw the circuit of the minimal expression using only NAND gates 16 (a) Show that if all the gates in a two – level AND-OR gate networks are replaced by NAND gates the output function does not change (b) Why does a good logic designer minimize the use of NOT gates? 17 Simplify the Boolean function F(A,B,C,D) = _ m (1,3,7,11,15) + _d (0,2,5) .if don’t care conditions are not taken care, What is the simplified Boolean function .What are your comments on it? Implement both circuits 18 (a) Show that if all the gate in a two – level OR-AND gate network are replaced by NOR gate, the output function does not change. (b) Implement Y = (A+C) (A+D’) ( A+B+C’) using NOR gates only 19 (a) F3 = f(a,b,c,d) = _ (2,4,5,6) F2 = f(a,b,c,d) = _ (2,3,,6,7) F1 = f(a,b,c,d) = _ (2,5,6,7) .Implement the above Boolean functions (i) When each is treated separately and WWW.VIDYARTHIPLUS.COM (ii)When sharing common term (b) Convert a NOR with an equivalent AND gate 20 Implement the Switching function whose octal designation is 274 using NAND gates only 21 Implement the Switching function whose octal designation is 274 using NOR gates only 22 (a) Show that the NAND operation is not distributive over the AND operation (b) Find a network of AND and OR gate to realize f(a,b,c,d) = _ m (1,5,6,10,13,14) 23 What is the advantages of using tabulation method? Determine the prime implicants of the following function using tabulation method F( W,X,Y,Z) = _(1,4,6,7,8,9,10,11,15) 23 (a) Explain about common postulates used to formulates various algebraic structures (b) Given the following Boolean function F= A”C + A’B + AB’C + BC Express it in sum of minterms & Find the minimal SOP expression 1. Design a 4 bit magnitude comparator to compare two 4 bit number 2. Construct a combinational circuit to convert given binary coded decimal number into an Excess 3 code for example when the input to the gate is 0110 then the circuit should generate output as 1001 3. Design a combinational logic circuit whose outputs are F1 = a’bc + ab’c and F2 = a’ + b’c + bc’ 4. (a) Draw the logic diagram of a *-bit 7483 adder (b) Using a single 7483, Draw the logic diagram of a 4 bit adder/sub tractor 5. Draw a diode ROM, which translates from BCD 8421 to Excess 3 code 6. Distinguish between Boolean addition and Binary addition 7. Realize a BCD to Excess 3 code conversion circuit starting from its truth table 8. (a) Design a full sub tractor 9. (b) How to it differ from a full sub tractor 10. Design a combinational circuit which accepts 3 bit binary number and converts its equivalent excess 3 codes 11. Derive the simplest possible expression for driving segment “a” through ‘g’ in an 8421 BCD to seven segment decoder for decimal digits 0 through 9 .Output should be active high (Decimal 6 should be displayed as 6 and decimal 9 as 9) 12. Write the HDL description of the circuit specified by the following Boolean function (i) Y= (A+B+C) (A’+B’+C’) (ii) F= (AB’ + A’B) (CD’+C’D) (iii) Z = ABC + AB’ + A(D+B) (iv) T= [(A+B} {B’+C’+D’)] 13. Design 16 bit adder using 4 7483 ICs Part B 1. Implement the switching function F= _(0,1,3,4,7) using a 4 input MUX and explain 2. Explain how will build a 64 input MUX using nine 8 input MUXs 3. State the advantages of complex MSI devices over SSI gates 4. Implement the switching function F(A,B,C) = _ ( ,2,4,5) using the DEMUX 74156 5. Implement the switching function F= _(0,1,3,4,12,14,15) using an 8 input MUX 6. Explain how will build a 16 input MUX using only 4 input MUXs 7. Explain the operation of 4 to 10 line decoder with necessary logic diagram 8. Draw a neat sketch showing implementation of Z1 = ab’d’e + a’b’c’e’ + bc + de , Z2 = a’c’e, Z3 = bc +de+c’d’e’+bd and Z4 = a’c’e +ce using a 5*8*4 PLA 9. Implement the switching functions: Z1 = ab’d’e + a’b’c’e’ + bc + de , Z2 = a’c’e, Z3 = bc +de+c’d’e’+bd and Z4 = a’c’e +ce Using a 5*8*4 PLA 10 Design a switching circuit that converts a 4 bit binary code into a 4 bit Gray code using WWW.VIDYARTHIPLUS.COM ROM array 11.Design a combinational circuit using a ROM ,that accepts a 3- bit number and generates an output binary number equal to the square of the given input number 1 Draw the state diagram and characteristics equation of T FF, D FF and JK FF 2 (a) What is race around condition? How is it avoided? (b) Draw the schematic diagram of Master slave JK FF and input and output waveforms.Discuss how it prevents race around condition 3 Explain the operation of JK and clocked JK flip-flops with suitable diagrams 4 Draw the state diagram of a JK flip- flop and D flip – flop 5 Design and explain the working of a synchronous mod – 3 counter 6 Design and explain the working of a synchronous mod – 7 counter 7 Design a synchronous counter with states 0,1, 2,3,0,1 …………. Using JK FF 8 Using SR flip flops, design a parallel counter which counts in the sequence 000,111,101,110,001,010,000 …………. 9 Using JK flip flops, design a parallel counter which counts in the sequence 000,111,101,110,001,010,000 …………. 10 (a) Discuss a decade counter and its working principle (b) Draw as asynchronous 4 bit up-down counter and explain its working 11 (a) How is the design of combinational and sequential logic circuits possible with PLA? (b) Mention the two models in a sequential circuit and distinguish between them 12 Design a modulo 5 synchronous counter using JK FF and implement it. Construct its timing diagram 12 A sequential machine has one input line where 0’s and 1’s are being incident. The WWW.VIDYARTHIPLUS.COM machine has to produce a output of 1 only when exactly two 0’s are followed by a ‘1’ or exactly two 1’s are followed by a ‘0’.Using any state assignment and JK flipflop,synthesize the machine 13 Using D flip –flop ,design a synchronous counter which counts in the sequence 000, 001, 010, 011, 100, 1001,110,111,000 15 Using JK flip-flops, design a synchronous sequential circuit having one and one output. the output of the circuit is a 1 whenever three consecutive 1’s are observed. Otherwise the output is zero 14 Design a binary counter using T flip – flops to count in the following sequences: (i) 000,001,010,011,100,101,110,111,000 (ii) 000,100,111,010,011,000 15 (a) Design a synchronous binary counter using T flip – flops (b) Derive the state table of a serial binary adder 17. Design a 3 bit binary Up-Down counter 18. (i) Summarize the design procedure for synchronous sequential circuit (ii) Reduce the following state diagram UNIT – V ASYNCHRONOUS 1. What is the objective of state assignment in asynchronous circuit? Give hazard – free realization for the following Boolean function f(A,B,C,D) = _M(0,2,6,7,8,10,12) 2. Summarize the design procedure for asynchronous sequential circuit a. Discuss on Hazards and races b. What do you know on hardware descriptive languages? 3. Design an asynchronous sequential circuit with 2 inputs X and Y and with one output Z Wherever Y is 1, input X is transferred to Z .When Y is 0; the output does not change for any change in X.Use SR latch for implementation of the circuit 4. Develop the state diagram and primitive flow table for a logic system that has 2 inputs,x and y and an output z.And reduce primitive flow table. The behavior of the circuit is stated as follows. Initially x=y=0. Whenever x=1 and y = 0 then z=1, whenever x = 0 and y = 1 then z = 0.When x=y=0 or x=y=1 no change in z ot remains in the previous state. The logic system has edge triggered inputs with out having a clock .the logic system changes state on the rising edges of the 2 inputs. Static input values are not to have any effect in changing the Z output 5. Design an asynchronous sequential circuit with two inputs X and Y and with one output Z. Whenever Y is 1, input X is transferred to Z.When Y is 0,the output does not change for any change in X. WWW.VIDYARTHIPLUS.COM 6. Obtain the primitive flow table for an asynchronous circuit that has two inputs x,y and one output Z. An output z =1 is to occur only during the input state xy = 01 and then if the only if the input state xy =01 is preceded by the input sequence. 7. A pulse mode asynchronous machine has two inputs. It produces an output whenever two consecutive pulses occur on one input line only .The output remains at ‘1’ until a pulse has occurred on the other input line. Draw the state table for the machine. 8. (a) How will you minimize the number of rows in the primitive state table of an incompletely specified sequential machine (b) State the restrictions on the pulse width in a pulse mode asynchronous sequential machine 9. Construct the state diagram and primitive flow table for an asynchronous network that has two inputs and one output. The input sequence X1X2 = 00,01,11 causes the output to become 1.The next input change then causes the output to return to 0.No other inputs will produce a 1 output --------------------------------------------------------*************-------------------
Posted on: Tue, 26 Nov 2013 06:42:35 +0000
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