vo dormi vo sonha com issso /* 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux. Maintained by Jeff Garzik Copyright 2000,2001 Jeff Garzik Much code comes from Donald Beckers rtl8139.c driver, versions 1.13 and older. This driver was originally based on rtl8139.c version 1.07. Header of rtl8139.c version 1.13: ---------- Written 1997-2001 by Donald Becker. This software may be used and distributed according to the terms of the GNU General Public License (GPL), incorporated herein by reference. Drivers based on or derived from this code fall under the GPL and must retain the authorship, copyright and license notice. This file is not a complete program and may only be used when the entire operating system is licensed under the GPL. This driver is for boards based on the RTL8129 and RTL8139 PCI ethernet chips. The author may be reached as becker@scyld, or C/O Scyld Computing Corporation 410 Severn Ave., Suite 210 Annapolis MD 21403 Support and updates available at scyld/network/rtl8139.html Twister-tuning table provided by Kinston . ---------- This software may be used and distributed according to the terms of the GNU General Public License, incorporated herein by reference. Contributors: Donald Becker - he wrote the original driver, kudos to him! (but please dont e-mail him for support, this isnt his driver) Tigran Aivazian - bug fixes, skbuff free cleanup Martin Mares - suggestions for PCI cleanup David S. Miller - PCI DMA and softnet updates Ernst Gill - fixes ported from BSD driver Daniel Kobras - identified specific locations of posted MMIO write bugginess Gerard Sharp - bug fix, testing and feedback David Ford - Rx ring wrap fix Dan DeMaggio - swapped RTL8139 cards with me, and allowed me to find and fix a crucial bug on older chipsets. Donald Becker/Chris Butterworth/Marcus Westergren - Noticed various Rx packet size-related buglets. Santiago Garcia Mantinan - testing and feedback Jens David - 2.2.x kernel backports Martin Dennett - incredibly helpful insight on undocumented features of the 8139 chips Jean-Jacques Michel - bug fix Tobias Ringström - Rx interrupt status checking suggestion Andrew Morton - Clear blocked signals, avoid buffer overrun setting current->comm. Submitting bug reports: rtl8139-diag -mmmaaavvveefN output enable RTL8139_DEBUG below, and look at dmesg or kernel log See 8139too.txt for more details. ----------------------------------------------------------------------------- 2001/09/21 Comments by ShuChen Shao 1.This driver is originally based on 8139too.c version 0.9.15. 2.It has been enhanced to support RTL8139C+ PCI ethernet chips and tested in 2.4.2 kernel. 3.RTL8139C+ PCI ethernet chips is set to support C+ mode by default. If FORCE_C_Mode below is enable, the RTL8139C+ chip will be forced to support C mode after reboot. 4.This program can be compiled at /usr/src/linux-2.4.2/drivers/net/ using the attached Makefile. And the object file named 8139too.o should be moved to the directory /lib/modules/2.4.2-2/kernel/drivers/net/ */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include //for copy_from_user #include #if LINUX_VERSION_CODE < 0x20407 #else #include #include #endif #define RTL8139CP_VERSION 1.6.0 #define MODNAME 8139too #define RTL8139_DRIVER_NAME MODNAME Fast Ethernet driver RTL8139CP_VERSION #define PFX MODNAME : #undef RTL8139_PROC_DEBUG #undef FORCE_CPlus_Mode #undef FORCE_C_Mode /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */ #ifdef CONFIG_8139TOO_PIO #define USE_IO_OPS 1 #endif /* define to 1 to enable copious debugging info */ #undef RTL8139_DEBUG /* define to 1 to disable lightweight runtime debugging checks */ #undef RTL8139_NDEBUG #ifdef RTL8139_DEBUG /* note: prints function name for you */ # define DPRINTK(fmt, args...) printk(KERN_DEBUG %s: fmt, __FUNCTION__ , ## args) #else # define DPRINTK(fmt, args...) #endif #ifdef RTL8139_NDEBUG # define assert(expr) do {} while (0) #else # define assert(expr) \ if(!(expr)) { \ printk( Assertion failed! %s,%s,%s,line=%d\n, \ #expr,__FILE__,__FUNCTION__,__LINE__); \ } #endif /* A few user-configurable values. */ /* media options */ #define MAX_UNITS 8 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ static int max_interrupt_work = 20; /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). The RTL chips use a 64 element hash table based on the Ethernet CRC. */ static int multicast_filter_limit = 32; /* Size of the in-memory receive ring. */ #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */ #define RX_BUF_LEN (8192 mtu+14+4).*/ #define MIN_ETH_FRAME_SIZE 60 #define MAX_ETH_FRAME_SIZE 1536 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */ #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC) /* PCI Tuning Parameters Threshold is bytes transferred to chip before transmission starts. */ #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ #define RX_FIFO_THRESH 0 /* Rx buffer level before first PCI xfer. */ #define RX_DMA_BURST 7 /* Maximum PCI burst, 6 is 1024 */ #define TX_DMA_BURST 6 /* Maximum PCI burst, 6 is 1024 */ /* Operational parameters that usually are not changed. */ /* Time in jiffies before concluding the transmitter is hung. */ #define TX_TIMEOUT (6*HZ) //////////////////////////////////////////////////////////////////// //for 8139C+ only #define NUM_CP_TX_DESC 64 /* Number of Tx descriptor registers for C+*/ #define NUM_CP_RX_DESC 64 /* Number of Rx descriptor registers for C+*/ #define CP_RX_BUF_SIZE 2000 #define CPlusEarlyTxThld 0x06 #define CPlusChecksumOffload 0x00070000 //////////////////////////////////////////////////////////////////// enum { HAS_MII_XCVR = 0x010000, HAS_CHIP_XCVR = 0x020000, HAS_LNK_CHNG = 0x040000, }; #define RTL_MIN_IO_SIZE 0x80 #define RTL8139B_IO_SIZE 256 #define RTL8129_CAPS HAS_MII_XCVR #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG typedef enum { RTL8139 = 0, RTL8139_CB, SMC1211TX, /*MPX5030,*/ DELTA8139, ADDTRON8139, DFE538TX, RTL8129, } board_t; /* indexed by board_t, above */ static struct { const char *name; u32 hw_flags; } board_info[] __devinitdata = { { RealTek RTL8139CP Fast Ethernet, RTL8139_CAPS }, { RealTek RTL8139B PCI/CardBus, RTL8139_CAPS }, { SMC1211TX EZCard 10/100 (RealTek RTL8139), RTL8139_CAPS }, /* { MPX5030, Accton MPX5030 (RealTek RTL8139), RTL8139_CAPS },*/ { Delta Electronics 8139 10/100BaseTX, RTL8139_CAPS }, { Addtron Technolgy 8139 10/100BaseTX, RTL8139_CAPS }, { D-Link DFE-538TX (RealTek RTL8139), RTL8139_CAPS }, { INTELBRAS PEF132 Fast Ethernet Adapter, RTL8129_CAPS }, }; static struct pci_device_id rtl8139_pci_tbl[] __devinitdata = { {0x146C, 0x146C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139_CB }, {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX }, /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/ {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 }, {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 }, {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE538TX }, {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 }, /* some crazy cards report invalid vendor ids like * 0x0001 here. The other ids are valid and constant, * so we simply dont match on the main vendor id. */ {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 }, {0,} }; MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl); /* The rest of these values should never change. */ /* Symbolic offsets to registers. */ enum RTL8139_registers { MAC0 = 0, /* Ethernet hardware address. */ MAR0 = 8, /* Multicast filter. */ TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */ TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ RxBuf = 0x30, RxEarlyCnt = 0x34, RxEarlyStatus = 0x36, ChipCmd = 0x37, RxBufPtr = 0x38, RxBufAddr = 0x3A, IntrMask = 0x3C, IntrStatus = 0x3E, TxConfig = 0x40, ChipVersion = 0x43, RxConfig = 0x44, Timer = 0x48, /* A general-purpose counter. */ RxMissed = 0x4C, /* 24 bits valid, write clears. */ Cfg9346 = 0x50, Config0 = 0x51, Config1 = 0x52, FlashReg = 0x54, MediaStatus = 0x58, Config3 = 0x59, Config4 = 0x5A, /* absent on RTL-8139A */ HltClk = 0x5B, MultiIntr = 0x5C, TxSummary = 0x60, BasicModeCtrl = 0x62, BasicModeStatus = 0x64, NWayAdvert = 0x66, NWayLPAR = 0x68, NWayExpansion = 0x6A, /* Undocumented registers, but required for proper operation. */ FIFOTMS = 0x70, /* FIFO Control and test. */ CSCR = 0x74, /* Chip Status and Configuration Register. */ PARA78 = 0x78, PARA7c = 0x7c, /* Magic transceiver parameter register. */ Config5 = 0xD8, /* absent on RTL-8139A */ // For C+ Registers CPlusTxPoll=0xD9, CPlusCmd=0xE0, CPlusRxStartAddr=0xE4, CPlusTxStartAddr=0x20, CPlusEarlyTxThldReg=0xEC, }; enum ClearBitMasks { MultiIntrClear = 0xF000, ChipCmdClear = 0xE2, Config1Clear = (1
Posted on: Tue, 29 Oct 2013 00:57:43 +0000
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