Hiring in Physical Design, Methodology & Implementation TOP Front-Line MNCs; Please rush your CV @ newsoft@nsoftindia # 1. Physical Design - Sr. Engineer/ Lead Job Function # Physical implementation of high performance processor, DSP and graphics cores. # Activities include floorplanning, place and route, clock tree synthesis, timing closure, power analysis, Physical verification. # Interact with the RTL design and synthesis teams to achieve the best quality of results in terms of Performance/area/power. Skills/Experience # 3-9 years experience in ASIC physical design. # Experience in SOC Place/route tools Magma TALUS or Synopsys ICC is required. # Knowledge of PTSI static timing tool suite , Calibre Physical verification tool suite is a PLUS. # Semi custom place and route implementation experience is a PLUS. # Circuit design expertise and exposure to spice circuit simulations is a PLUS. Education Requirements Required: Bachelors, Computer Engineering and/or Computer Science and/or Electrical Engineering Required: Masters, Computer Engineering and/or Computer Science and/or Electrical Engineering # 2. Implementation : Engineer/ Sr. Engineer/ Lead # B.Tech or Masters in Electronics plus 3-8 Years of relevant experience in Implementation / Physical design # Hands on experience in Synthesis and/or Custom design # Working knowledge of Timing Analysis, physical verification, signal integrity issues # Strong domain expertise in one or more areas of physical design # PERL, Unix & TCL coding skills # 3. STA / Timing Engineer/ Lead (3-8 Yrs ) B.Tech/Masters degree in electronics. Worked on full chip synthesis using Synopsys DC / Cadence RC compiler Experience with Synopsys PrimeTime Understanding of Verilog/VHDL RTL constructs Exp. to DDR2/3, high speed I/O timing Interface or similar # 4. Methodology - Engineers/ Lead Responsible to evaluate, define, implement and sustain state-of-the-art design methodology for ASIC engineering team. Responsible for creating differentiators, from a Power/ Performance/ Area Standpoint & Interfacing with External stakeholders like Vendors and ASIC customers to understand their needs and also to explain our methodology and roadmap to them. Exposure to cross-vendor EDA design flows, Candidate should have taped out multiple leading edge designs and should be fully conversant with design issues, especially posed by deep sub-micron geometries such as 65 , 45 and 32 nm. Expertise in ASIC PD activities or DFT /STA activities.
Posted on: Thu, 28 Nov 2013 09:16:48 +0000
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