What is Formal Verification ??? Around 70% of the overall design time and cost is spent on verification and validation. It becomes very important to verify the correctness of the circuits. Modern complex designs contain several hundred million transistors. Verification of such a complex system in a shorter span of time becomes a dominating factor before it goes silicon level. Several Formal Verification methods have been proposed and are under research as an alternative to classical simulation techniques, since it can’t guarantee sufficient coverage of the design. In addition to this simulation is a slow process. Formal Verification (FV) techniques ensure 100% functional correctness and they are more reliable and cost effective, less time consuming. The main concept of FV is not to simulate some vectors, instead prove the functional correctness of a design. There are different proof methodologies employed, the most common being Equivalence Checking (EC) methodology. The basic methodology used in most of the industry verification tools, known as Binary Decision Diagram (BDD) and Satisfiability (SAT) solvers, come under this category. These traditional methods fail to handle complex circuits efficiently. Hence new trends like SAT based Symbolic Model Checking are emerging which fall under Model Checking (MC) (Also known as Property Checking (PC)) methodology. New techniques like Bounded Model Checking (BMC) based on SAT solvers are promising better efficient methods of Formal Verification. Hybrid Formal Verification methods are under investigation which employs strength of respective Formal Verification models. Each of these methods has their own pros and cons which will be discuss later. #Formal_Verification #Equivalence_Checking #Binary_Decision_Diagram #SAT #Model_Checking #Property_checking #Bounded_Model_Checking #Hybrid_Formal_Verification Next update detail knowledge of each term (follow us) : goo.gl/fA8Fx9
Posted on: Tue, 05 Nov 2013 08:43:13 +0000
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